FIG. 1A illustrates the test architecture of a conventional 1149.1 TAP 100. The TAP includes a TAP controller 110, instruction register 112, and set of data registers. The set of data registers includes; (1) an internal scan register 114, (2) an in-circuit emulation (ICE) register 116, (3) an in-system programming (ISP) register 118, (4) a boundary scan register 120, and (5) a bypass register 122. Of the data registers, the boundary scan register and bypass register are defined by the IEEE 1149.1 standard. The other shown data registers are not defined by 1149.1, but can exist as optional data registers within the data register section of the 1149.1 standard architecture. The TAP controller responds to a protocol input on the TCK 124 and TMS 126 inputs to coordinate serial communication through either the instruction register from TDI 101 to TDO 102, or through a selected one of the data registers from TDI to TDO. The TRST 128 input is used to initialize the TAP to a known state. The operation of the TAP is well known
FIG. 1B illustrates an IC or intellectual property core circuit 130 incorporating the TAP 100 and its TDI, TDO, TMS, TCK, and TRST interface. A core circuit is a complete circuit function that is embedded within an IC, such as a DSP or CPU. FIGS. 1C-1G illustrate the association between each of the data registers of FIG. 1A and the target circuit they connect to.
The data registers are commonly connected at their serial input to TDI 101. The data registers are separately connected at their respective serial outputs 104-108 to associated inputs of multiplexer 103, so that they can be individually selected by an instruction to output data on TDO 102, through FF 132, during a data register scan.
FIG. 2 illustrates the state diagram of the TAP controller of FIG. 1A. The TAP controller is clocked by the TCK input and transitions through the states of FIG. 2 in response to the TMS input. As seen in FIG. 2, the TAP controller state diagram consists of four key state operations, (1) a Reset/RunTest Idle state operation 200 where the TAP controller goes to either enter a reset state 202, a run test state, or an idle state 204, (2) a Data or Instruction Scan Select state operation 206 the TAP controller may transition through to select a data register (DR) 208 or instruction register (IR) 210 scan operation, or return to the reset state, (3) a Data Register Scan Protocol state operation 212 where the TAP controller goes when it communicates to a selected data register, and (4) an Instruction Register Scan Protocol state operation 214 where the TAP controller goes when it communicates to the instruction register. The operation of the TAP controller is well known.
FIG. 3A illustrates a conventional internal scan test port interface 300 to an internal scan register 301. The scan test port includes a scan input (SI) 302, scan output (SO) 304, scan enable (SE) 306, capture select (CS) 308, and clock (CK) 310 inputs. The CK input may be the circuits functional clock or it may be a dedicated test clock input. The SE input is used to place the circuit in a scan test mode. Placing the circuit in a scan test mode may involve conditioning a circuit input for providing the SI input, conditioning a circuit output for providing the SO output, and conditioning a circuit input for the CS input, as indicated by the dashed circles 312, 314, 316. The SE input may also be used to condition the scan register and logic circuitry 318 such that it operates in a safe mode during the test. For example, it may condition the logic circuit such that no contention occurs between logic outputs during the scan test. In test mode, SI provides the serial input to the internal scan register, SO provides the serial output from the internal scan register, CS provides the control input protocol to cause the internal scan register to capture response data from the logic circuitry then shift data through the scan register from SI to SO to unload the captured response data and load the next stimulus data to be applied to the logic circuitry.
FIG. 3B illustrates an IC or core 320 incorporating the scan test port (STP) 300 of FIG. 3A. For ICs, the SI, SO, and CS signals are typically shared with functional signal pins to save pin count while the SE signal is typically a dedicated IC pin so that it can be accessed to switch the shared pins between their functional and SI, SO, CS test modes. The CK signal may be the ICs functional clock or it may be a dedicated test clock. For cores, the SE, SI, SO, CS, and CK signals may all be dedicated for scan test access since cores typically do not suffer from the pin count problem that ICs do. The role of the SE signal on cores may only be to condition the scan register and logic circuitry for the previously mentioned safe operation during the test, instead of being used to switch inputs and outputs between functional and test mode as mentioned for the IC scan test port SI, SO, and CS signals.
FIG. 3C illustrates an IC or core 330 including both the STP 300 of FIG. 3A and the TAP 100 of FIG. 1A. In FIG. 3C it is seen that the TAP and the STP require different interface signals since their input and output operations are based on different serial interface protocols.
FIG. 4 illustrates a system IC 400 consisting of cores 1−N 402. Each core includes a TAP interface 100 and a STP interface 300. The core TAPs are serially connected, via a first scan path wiring bus 410, to allow a tester to access the TAPs of embedded circuits in the cores, such as the embedded target circuits of FIGS. 1C-1F. The STPs are serially connected, via a second scan path wiring bus 420, to allow a tester to access the STPs of embedded internal scan circuitry of the cores, such as the scan circuitry of FIG. 3A. From FIG. 4 it is seen that the system IC requires two test interfaces, one for the core TAPs and another for the core STPs. Further, the IC requires two separate internal scan path wiring buses, one scan path wiring bus 410 for the core TAPs and another scan path wiring bus 420 for the core STPs.